In the design of a mainframe CPU employing VLSI technology, it is desirable to limit the number of different types of VLSI chips employed in order to contain the design task within manageable bounds. However, it is also highly desirable to provide powerful and reliable error detection and handling features, and this requirement has mandated the provision of various circuits, firmware and software to sense and resolve the diverse types of errors which may occur in operation.
Among the possible error conditions encountered in a VLSI central processing unit are those in which one of the modules of a BPU, performing routine data manipulation such as calculating, simply reaches an incorrect result. It can be shown that employing built-in error detection (e.g., parity checking) in the circuitry of a BPU results in a significant increase in circuitry. This effect not only substantially extends the design effort required to develop a BPU, but also increases the "real estate" or space occupied by the BPU and its support circuitry and consequently that of the CPU. It also may significantly degrade the performance of the most "time-critical" circuitry in the BPU.